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Integrated Circuit Systems, Inc.
ICS9248-138
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 810/810E and Solano type chipset. Output Features: * 2- CPUs @ 2.5V * 9 - SDRAM @ 3.3V, including 1 free running * 7 - PCICLK @ 3.3V * 1 - IOAPIC @ 2.5V, * 3 - 3V66MHz @ 3.3V * 2 - 48MHz, @ 3.3V fixed. * 1 - 24/48MHz, @3.3V selectable by I2C * 1 - REF @v3.3V, 14.318MHz. Features: * Up to 200MHz frequency support * Support FS0-FS4 strapping status bit for I2C read back. * Support power management: Through Power down Mode from I2C programming. * Spread spectrum for EMI control ( 0.25% center). * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: <175ps * SDRAM - SDRAM: < 250ps * 3V66 - 3V66: <175ps * PCI - PCI: <500ps * For group skew specifications, please refer to group timing relationship.
Pin Configuration
1
*SEL24_48#/REF0 VDDREF X1 X2 GNDREF GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI 1 *FS0/PCICLK0 1 **FS1/PCICLK1 GNDPCI PCICLK2 PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 GNDPCI PD# SCLK SDATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDLAPIC 1 IOAPIC VDDLCPU CPUCLK0 CPUCLK1 GNDLCPU GNDSDR SDRAM0 SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 SDRAM5 GNDSDR SDRAM6 SDRAM7 SDRAM_F VDDSDR GND48 24_48MHz/FS2** 48MHz/FS3* 1 48MHz/FS4* VDD48
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD. ** These inputs have a 120K pull down to GND. 1 These are double strength.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum
2
Functionality
48MHz [1:0] 24_48MHz
FS4 FS3 FS2 FS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
REF0
CPU DIVDER
2
CPUCLK [1:0]
SDRAM DIVDER
8
SDRAM [7:0] SDRAM_F
SEL24_48# Control SDATA SCLK FS[4:0] PD# Config. Reg. Logic
IOAPIC DIVDER
IOAPIC
PCI DIVDER
7
PCICLK [6:0]
CPU (MHz) 66.67 66.87 68.67 71.34 100.00 100.30 103.00 107.00 133.33 133.73 137.33 120.00 133.33 133.73 137.33 120.00
SDRAM (MHz) 100.00 100.30 103.00 107.00 100.00 100.30 103.00 107.00 133.33 133.73 137.33 120.00 100.00 100.30 103.00 90.00
ICS9248-138
3V66 (MHz) 66.67 66.87 68.67 71.34 66.67 66.87 68.67 71.34 66.67 66.87 68.67 60.00 66.67 66.87 68.67 60.00
PCICLK (MHz) 33.33 33.43 34.33 35.66 33.33 33.43 34.33 35.66 33.33 33.43 34.33 30.00 33.33 33.43 34.33 30.00
I OA P I C (MHz) 16.67 16.72 17.16 17.83 16.67 16.72 17.17 17.84 16.67 16.72 17.17 15.00 16.67 16.72 17.17 15.00
3V66 DIVDER
3V66 [2:0]
3
1 1 1 1
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1 1 1 1
0 1 0 1
1 0 1 1
0 1 1 0
160.00 160.00 166.67 166.67
160.00 120.00 166.67 125.00
80.00 80.00 83.34 83.34
40.00 40.00 41.67 41.67
20.00 20.00 20.84 20.84
Additional frequencies selectable through I2C programming.
ICS9248-138
General Description
The ICS9248-138 is the single chip clock solution for designs using the 810/810E and Solano style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-138 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER 1 2, 10, 11, 18, 25, 30, 38 3 4 5, 6, 14, 21, 29, 34, 42 9, 8, 7 12 13 20, 19, 17, 16, 15 PIN NAME SEL24_48MHz# REF0 VDD X1 X2 GND 3V66 [2:0] FS0 PCICLK0 FS1 PCICLK1 PCICLK [6:2] PD# SCLK SDATA FS4 48MHz FS3 48MHz TYPE IN OUT PWR IN OUT PWR OUT IN OUT IN OUT OUT IN IN IN IN OUT IN OUT IN DESCRIPTION Logic inputs frequency select I/O/USB output, When a "0" is latched, output frequency = 48MHz When a "1" is latched, output frequency = 24MHz 14.318 MHz reference clock. 3.3V Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48MHz output Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Ground pin for 3V outputs. 3.3V Clocks Frequency select pin. PCI clock output Frequency select pin. PCI clock output PCI clock outputs. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Clock input of I2C input, 5V tolerant input Data input for I2C serial input, 5V tolerant input Frequency select pin. 48MHz output clocks Frequency select pin. 48MHz output clocks Frequency select pin.
22 23 24
26 27 28 31 32, 33, 35, 36, 37, 39, 40, 41, 43 44, 45 46 47 48
FS2 24_48MHz
SDRAM_F SDRAM [7:0] GNDLCPU CPUCLK [1:0] VDDLCPU IOAPIC VDDLAPIC
OUT
OUT OUT PWR OUT PWR OUT PWR
24 or 48MHz output
Free running SDRAM - used for feed back to chipset, should remain on always. SDRAM clock outputs Ground pin for the CPU clocks. CPU clock outputs. Power pin for the CPUCLKs. 2.5V 2.5V clock output Power pin for the IOAPIC. 2.5V
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ICS9248-138
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Description CPUCLSDRAM 3V66 K (MHz) (MHz) FS4 FS3 FS2 FS1 FS0 (MHz) 0 0 0 0 0 66.67 100.00 66.67 0 0 0 0 1 66.87 100.30 66.87 0 0 0 1 0 68.67 103.00 68.67 0 0 0 1 1 71.34 107.00 71.34 0 0 1 0 0 100.00 100.00 66.67 0 0 1 0 1 100.30 100.30 66.87 0 0 1 1 0 103.00 103.00 68.67 0 0 1 1 1 107.00 107.00 71.34 0 1 0 0 0 133.33 133.33 66.67 0 1 0 0 1 133.73 133.73 66.87 0 1 0 1 0 137.33 137.33 68.67 0 1 0 1 1 120.00 120.00 60.00 0 1 1 0 0 133.33 100.00 66.67 0 1 1 0 1 133.73 100.30 66.87 Bit 0 1 1 1 0 137.33 103.00 68.67 2, 7:4 0 1 1 1 1 120.00 90.00 60.00 1 0 0 0 0 136.00 136.00 68.00 1 0 0 0 1 140.00 140.00 70.00 1 0 0 1 0 142.67 142.67 71.34 1 0 0 1 1 145.33 145.33 72.67 1 0 1 0 0 136.00 102.00 68.00 1 0 1 0 1 140.00 105.00 70.00 1 0 1 1 0 142.67 107.00 71.34 1 0 1 1 1 145.33 109.00 72.67 1 1 0 0 0 146.67 146.67 73.34 1 1 0 0 1 153.33 153.33 76.67 1 1 0 1 0 160.00 160.00 80.00 1 1 0 1 1 166.67 166.67 83.34 1 1 1 0 0 146.67 110.00 73.34 1 1 1 0 1 160.00 120.00 80.00 1 1 1 1 0 166.67 125.00 83.34 1 1 1 1 1 200.00 200.00 66.67 0 - Frequency is selected by hardware select, Latched Inputs Bit 3 1 - Frequency is selected by Bit 2, 6:4 0 - Normal Bit 1 1 - Spread Spectrum Enabled 0.25% Center Spread 0 - Running Bit 0 1- Tristate all outputs bit2 bit7 bit6 bit5 bit4 Bit PWD PCICLK IOAPIC (MHz) (MH) 33.33 33.43 34.33 35.67 33.33 33.43 34.33 35.67 33.33 33.43 34.33 30.00 33.33 33.43 34.33 30.00 34.00 35.00 35.67 36.33 34.00 35.00 35.67 36.33 36.67 38.33 40.00 41.67 36.67 40.00 41.67 33.33 16.67 16.72 17.16 17.83 16.67 16.72 17.17 17.84 16.67 16.72 17.17 15.00 16.67 16.72 17.17 15.00 17.00 17.50 17.84 18.17 17.00 17.50 17.84 18.17 18.34 19.17 20.00 20.84 18.34 20.00 20.84 16.67 Spread Precentage 0 to -0.5% Down Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0 to -0.5% Down Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0 to -0.5% Down Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0 to -0.5% Down Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread 0.25% Center Spread
(0,0001)
0 0 0
Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
I2C is a trademark of Philips Corporation
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ICS9248-138
Byte 1: SDRAM Control Register (1= enable, 0 = disable)
Byte 2: PCI, Control Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD X X 31 1 32 1 33 1 35 1 36 1 37 1
DESCRIPTION FS2# FS1# SDRAM_F SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD X 20 1 19 1 17 1 16 1 15 1 13 1 12 1
DESCRIPTION FS0# PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Byte 3: 3V66, Control Register (1= enable, 0 = disable)
Byte 4: Control Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD X 1 1 1 1 7 1 8 1 9 1
DESCRIPTION FS4# Reser ved Reser ved Reser ved Reser ved 3V66-0 3V66-1 3V66-2
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD 1 1 1 1 1 27 1 26 1 28 1
DESCRIPTION Reser ved Reser ved Reser ved Reser ved Reser ved 48MHz-0 48MHz-1 24_48MHz
Byte 5: Control Register (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Notes:
PIN# PWD X 1 1 47 1 44 1 45 1 39 1 40 1 41 1
DESCRIPTION (SEL24_48#)# REF0 IOAPIC CPUCLK1 CPUCLK0 SDRAM2 SDRAM1 SDRAM0
Byte 6: Control Register (1= enable, 0 = disable) BIT PIN# PWD DESCRIPTION Bit7 0 Reser ved (Note) Bit6 0 Reser ved (Note) Bit5 0 Reser ved (Note) Bit4 0 Reser ved (Note) Bit3 0 Reser ved (Note) Bit2 1 Reser ved (Note) Bit1 1 Reser ved (Note) Bit0 0 Reser ved (Note)
Note: Don't write into this register, writing into this register can cause malfunction. This Byte becomes the Byte Count for Readback, so it cannot be seen as data.
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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ICS9248-138
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 5.5 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Group Timing Relationship Table
Group CPU 66MHz SDRAM 100MHz Offset CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to PCI USB & DOT 2.5ns 7.5ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 100MHz SDRAM 100MHz Offset 5.0ns 5.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 133MHz SDRAM 100MHz Offset 0.0ns 0.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 133MHz SDRAM 133MHz Offset 3.75ns 0.0ns 3.75ns 1.5 -3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance1 SYMBOL VIH V IL IIH I IL1 I IL2 I DD3.3OP I DD3.3PD Fi Lpin CIN Cout CINX Ttrans Ts TSTAB tPZH,t PZH t PLZ,t PZH CONDITIONS MIN 2 VSS - 0.3 -5 -5 -200 TYP MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 100 mA 600 14.318 7 Logic Inputs Out put pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From V DD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs) 1 1 5 6 45 3 3 3 10 10 mA MHz nH pF pF pF mS mS mS nS nS
V IN = V DD V IN = 0 V; Inputs with no pull-up resistors V IN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = 0 pF; With input address to Vdd or GND V DD = 3.3 V;
27
Transition Time1 Settling Time Delay
1 1
Clk Stabilization1
Guaranteed by design, not 100% tested in production.
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ICS9248-138
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP2B1 RDSN2B1 VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B
1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , V OH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 0.4 V, V OL = 2.0 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 13.5 13.5 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 45 45 0.4 -27 30 1.6 1.6 55 250 250 V V mA mA ns ns % ps ps
dt2B1 tsk2B1 tjcyc-cyc 1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 I OH1 I OL1 tr11 tf11 dt11 tsk11 tjcyc-cyc
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 12 2.4 -33 30 0.5 0.5 45
TYP
MAX UNITS 55 55 0.55 -33 38 2 2 55 175 500 V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
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ICS9248-138
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP4B1 RDSN4B1 VOH4\B VOL4B I OH4B IOL4B tr4B1 tf4B
1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -5.5 mA IOL = 9.0 mA VOH@ min = 1.0 V, VOH@ MAX = 2.375 V VOL@ MIN = 1.2 V, VOL@ MAX= 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, V OL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 9 9 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 30 30 0.4 -27 30 1.6 1.6 55 250 500 V V mA mA ns ns % ps ps
dt4B1 tsk41 tjcyc-cyc
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = V DDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP3 RDSN3 VOH3 VOL3 IOH3 IOL3 Tr31 Tf3
1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 2.0 V, V OH@ MAX=3.135 V VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.4 -54 54 0.4 0.4 45
TYP
MAX UNITS 24 24 0.4 -46 53 1.6 1.6 55 250 250 V V mA mA ns ns % ps ps
Dt31 Tsk31 tjcyc-cyc
Guaranteed by design, not 100% tested in production.
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ICS9248-138
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 I OH1 I OL1 tr11 tf11 dt11 tsk11 tjcyc-cyc
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 12 2.4 -33 30 0.5 0.5 45
TYP
MAX UNITS 55 55 0.55 -33 38 2 2 55 500 500 V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0
TA = 0 - 70C; VDD = V DDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP5 RDSN5 VOH5 VOL5 IOH5 IOL5 tr51 tf51 dt51 Tsk tjcyc-cyc 1 tjcyc-cyc 1
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = 1 mA IOL = -1 mA VOH @MIN=1 V, VOH@MAX= 3.135 V VOL@MIN=1.95 V, VOL@MIN=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V; Fixed Clocks VT = 1.5 V; Ref Clocks
MIN 20 20 2.4 -29 29
TYP
MAX UNITS 60 60 0.4 -23 27 4 4 V V mA mA ns ns % ps ps ps
45
55 250 500 1000
Guaranteed by design, not 100% tested in production.
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ICS9248-138
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Stop Bit
ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-138
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248138 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Fig. 1
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ICS9248-138
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK 3V66 PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-138
N
c
300 mil SSOP SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
A A1 b c D E E1 e h L N a VARIATIONS
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
A A1
N 48
-C-
D mm. MIN 15.75 MAX 16.00 MIN .620
D (inch) MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
e
b
SEATING PLANE .10 (.004) C
10-0034
Ordering Information
ICS9248yF-138
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0342C--08/26/03
12

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